SCL1C

Voltage regulator
SCL1C
generic
Opensource
CIM model
RMS
phasor
MRL4
Single phase
IEEE
dynawo
#236
Author

Erwan Guichard (DPS for RTE)

Published

August 10, 2024

IEEE SCL1C model

Context

This stator current limiter model first appeared in the IEEE Std 421.5-2016 [1].

Model use, assumptions, validity domain and limitations

This model is associated to one of the voltage regulators (types AC, DC, ST) defined by the IEEE Std 421.5-2016 [1].

The model provides two stator current limiter signals (one for overexcitation, the other for under excitation) for the purpose of takeover : the stator current limiter signals act as upper and lower limits (respectively) on the voltage regulator main signal which then becomes the excitation voltage.

Model inputs and outputs

The input signals are :

Variable Description Unit
\(itPu\) Complex stator current \(pu\) (base \(SnRef\), \(UNom\))
\(QGenPu\) Reactive power generated by the synchronous machine \(pu\) (base \(SnRef\))
\(utPu\) Complex stator voltage \(pu\) (base \(UNom\))

\(QGenPu\) follows the generator convention.

The output signals are :

Variable Description Unit
\(USclOelPu\) Stator current overexcitation limitation output voltage \(pu\) (base \(UNom\))
\(USclUelPu\) Stator current underexcitation limitation output voltage \(pu\) (base \(UNom\))

Model parameters

Parameter Description Unit Value (set 1) Value (set 2) Value (set 3)
\(IqMinPu\) Dead-band for reactive current \(pu\) (base \(SnRef\), \(UNom\)) \(0\) \(0\) \(0.1\)
\(ISclLimPu\) SCL terminal current pick up level \(pu\) (base \(SnRef\), \(UNom\)) \(1.05\) \(1.05\) \(1.05\)
\(K\) SCL timing characteristic factor \(pu\) \(1\) \(1\) \(1\)
\(KiOex\) SCL integral gain (overexcited range) \(pu\) \(0.2\) \(1\) \(0.0303\)
\(KiUex\) SCL integral gain (underexcited range) \(pu\) \(0.2\) \(1\) \(0.0303\)
\(KpOex\) SCL proportional gain (overexcited range) \(pu\) \(0\) \(0.1\) \(0\)
\(KpUex\) SCL proportional gain (underexcited range) \(pu\) \(0\) \(0.1\) \(0\)
\(Sw1\) Reactive current/reactive power selector \(-\) \(true\) \(true\) \(false\)
\(Sw2\) Fixed-time or inverse time selector \(-\) \(true\) \(false\) \(false\)
\(tDScl\) Fixed-time delay after pickup \(s\) \(0\) \(10\) \(0\)
\(tInv\) Inverse time delay after pickup \(s\) \(30\) \(0\) \(0\)
\(tIt\) Terminal current transducer equivalent time constant \(s\) \(0.005\) \(0.005\) \(0.1\)
\(tQScl\) Reactive current transducer equivalent time constant \(s\) \(0\) \(0\) \(0.02\)
\(VSclDb\) Dead-band for reactive power or power factor \(pu\) (base \(SnRef\)) \(0.1\) \(0.1\) \(0.1\)
\(VSclMaxPu\) SCL upper integrator limit \(pu\) (base \(UNom\)) \(1\) \(0.3\) \(0.2\)
\(VSclMinPu\) SCL lower integrator limit \(pu\) (base \(UNom\)) \(0\) \(0\) \(-0.1\)

The parameter sets correspond to a stator current limitation : - 1 : with an inverse time characteristic based on the reactive current of the generator; - 2 : with a fixed time characteristic based on the reactive current of the generator; - 3 : based on the reactive power output of the generator.

Model diagram

Figure 1: SCL1C model diagram

The input “\(ISclErrPu\) or \(0\)” of the OEL switch is determined as follows :

if (not \(Sw2\) and (\(ISclErrPu > 0\) for a duration \(> tDScl\))) or (\(Sw2\) and \(ISclInvPu > 0\)) if \(QGenPu > VSclDb\) input = \(ISclErrPu\) else input = \(0\) else input = \(0\)

The input “\(ISclErrPu\) or \(0\)” of the UEL switch is determined as follows :

if (not \(Sw2\) and (\(ISclErrPu > 0\) for a duration \(> tDScl\))) or (\(Sw2\) and \(ISclInvPu > 0\)) if \(QGenPu < -VSclDb\) input = \(ISclErrPu\) else input = \(0\) else input = \(0\)

Open source implementations

This model has been successfully implemented in :

Software URL Language Open-Source License Last consulted date Comments
Dynawo Link Modelica MPL v2.0 09/10/2024

References

1.
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