SCL2C

Authors: Erwan Guichard (DPS for RTE)

Reviewers: Lampros Papangelis (CRESYM)

IEEE SCL2C model

Context

This stator current limiter model first appeared in the IEEE Std 421.5-2016 (of Electrical & Engineers, 2016).

Model use, assumptions, validity domain and limitations

This model is associated to one of the voltage regulators (types AC, DC, ST) defined by the IEEE Std 421.5-2016 (of Electrical & Engineers, 2016).

The model provides two stator current limiter signals (one for overexcitation, the other for under excitation) for the purposes of :

  • takeover : the stator current limiter signals act as upper and lower limits (respectively) on the voltage regulator main signal which then becomes the excitation voltage ;
  • summation : the stator current limiter signals are added to the stator voltage deviation from the reference, thus being taken into account in the calculation of the excitation voltage.

Model inputs and outputs

The input signals are :

Variable Description Unit
itPu Complex stator current pu (base SnRef, UNom)
PGenPu Active power generated by the synchronous machine pu (base SnRef)
QGenPu Reactive power generated by the synchronous machine pu (base SnRef)
utPu Complex stator voltage pu (base UNom)

Both PGenPu and QGenPu follow the generator convention.

The output signals are :

Variable Description Unit
USclOelPu Stator current overexcitation limitation output voltage pu (base UNom)
USclUelPu Stator current underexcitation limitation output voltage pu (base UNom)

Model parameters

Parameter Description Unit Value (set 1) Value (set 2) Value (set 3)
C1 SCL exponent for calculation of first error - 0 0 0
C2 SCL exponent for calculation of second error - 2 2 2
FixedRd SCL fixed cooling-down time output pu -0.001 -0.001 -0.001
FixedRu SCL fixed delay time output pu 0 0 0
IInstPu SCL instantaneous stator current limit pu (base SnRef, UNom) 5 5 5
IInstUelPu Underexcited region instantaneous stator current limit pu (base SnRef, UNom) 1.1 1.1 1.1
ILimPu SCL thermal stator current limit pu (base SnRef, UNom) 1.1 1.1 1.1
IqOelMinPu SCL OEL minimum reactive current reference value pu (base SnRef, UNom) 0.02 0.02 0.02
IqUelMaxPu SCL UEL maximum reactive current reference value pu (base SnRef, UNom) -0.02 -0.02 -0.02
IResetPu SCL reset-reference, if inactive pu (base SnRef, UNom) 100 100 100
ITfPu SCL thermal reference for inverse time calculations pu (base SnRef, UNom) 1.1 1.1 1.1
IThOffPu SCL reset threshold value pu (base SnRef, UNom) 0.05 0.05 0.05
K1 SCL gain for calculation of first error pu 0 0 0
K2 SCL gain for calculation of second error pu 0.0333 0.0333 0.0333
KdOel Overexcited PID regulator differential gain pu 0 0 0
KdUel Underexcited PID regulator differential gain pu 0 0 0
KFb SCL timer feedback gain pu 0 0 0
KiOel Overexcited PID regulator integral gain pu 0 0 1
KiUel Underexcited PID regulator integral gain pu 0 0 1
KpOel Overexcited PID regulator proportional gain pu 0.5 250 0.3
KPRef SCL reference scaling factor based on active current pu 0 0 0
KpUel Underexcited PID regulator proportional gain pu 0.5 250 0.3
KIpOel Overexcited active current scaling factor pu 1 1 1
KIpUel Underexcited active current scaling factor pu 1 1 1
KIqOel Overexcited reactive current scaling factor pu 1 1 1
KIqUel Underexcited reactive current scaling factor pu 1 1 1
Krd SCL reference ramp-down rate pu/s (base SnRef, UNom) -1000 -1000 -1000
Kru SCL reference ramp-up rate pu/s (base SnRef, UNom) 1000 1000 1000
Kzru SCL thermal reference release threshold pu 0.99 0.99 0.99
Sw1 OEL reference ramp logic selection - false false false
tAScl SCL reference filter time constant s 0.04 0.04 0.04
tB1Oel Overexcited regulator lag time constant 1 s 0.1 12.5 0.1
tB1Uel Underexcited regulator lag time constant 1 s 0.1 12.5 0.1
tB2Oel Overexcited regulator lag time constant 2 s 0.1 0.1 0.1
tB2Uel Underexcited regulator lag time constant 2 s 0.1 0.1 0.1
tC1Oel Overexcited regulator lead time constant 1 s 0.1 1.5 0.1
tC1Uel Underexcited regulator lead time constant 1 s 0.1 1.5 0.1
tC2Oel Overexcited regulator lead time constant 2 s 0.1 0.1 0.1
tC2Uel Underexcited regulator lead time constant 2 s 0.1 0.1 0.1
tDOel Overexcited PID regulator differential time constant s 0.1 0.1 0.1
tDUel Underexcited PID regulator differential time constant s 0.1 0.1 0.1
tEnOel Overexcited activation delay time s 0.01 0.01 0.01
tEnUel Underexcited activation delay time s 0 0 0
tIpOel Overexcited active current time constant s 0.01 0.01 0.01
tIpUel Underexcited active current time constant s 0.01 0.01 0.01
tIqOel Overexcited reactive current time constant s 0.01 0.01 0.01
tIqUel Underexcited reactive current time constant s 0.01 0.01 0.01
tItScl Stator current transducer time constant s 0.01 0.01 0.01
tMax SCL timer maximum level s 1 1 1
tMin SCL timer minimum level s 0 0 0
tOff SCL reset delay time s 5 5 5
tScl SCL timer reference s 1 1 1
tVtScl Terminal voltage transducer time constant s 0.01 0.01 0.01
VInvMaxPu SCL maximum inverse time output pu 100 100 100
VInvMinPu SCL minimum inverse time output pu 0 0 0
VOel1MaxPu Maximum OEL output limit pu (base UNom) 10 10 0
VOel1MinPu Minimum OEL output limit pu (base UNom) -10 -8.7 -0.1
VOel2MaxPu Maximum OEL lead-lag 1 output limit pu (base UNom) 100 20 0
VOel2MinPu Minimum OEL lead-lag 1 output limit pu (base UNom) -100 -20 -0.1
VOel3MaxPu Maximum OEL PID output limit pu (base UNom) 100 100 0
VOel3MinPu Minimum OEL PID output limit pu (base UNom) -100 -100 -0.1
VtMinPu SCL OEL minimum voltage reference value pu (base UNom) 0.9 0.9 0.9
VtResetPu SCL OEL voltage reset value pu (base UNom) 0.8 0.8 0.8
VUel1MaxPu Maximum UEL output limit pu (base UNom) 10 10 0.1
VUel1MinPu Minimum UEL output limit pu (base UNom) -10 -8.7 0
VUel2MaxPu Maximum UEL lead-lag 1 output limit pu (base UNom) 100 100 0.1
VUel2MinPu Minimum UEL lead-lag 1 output limit pu (base UNom) -100 -100 0
VUel3MaxPu Maximum UEL PID output limit pu (base UNom) 100 100 0.1
VUel3MinPu Minimum UEL PID output limit pu (base UNom) -100 -100 0

The parameter sets correspond to a stator current limitation output :

  • 1 : with a takeover action at the AVR input;
  • 2 : with a takeover action at the AVR output;
  • 3 : added to the summation point in the AVR.

Model diagram

SCL2C

The SCL reference current is calculated with the following model :

SclReferenceCurrent

The SCL OEL activation logic has four inputs (on the left, from top to bottom, IOelActPu, tErr, IRefPu, at the top right corner, VtFiltPu) and one output (IOelBiasPu) calculated as follows :

if (VtFiltPu > VtMinPu and (tErr <= 0 or (IOelActPu > IOelRefPu for a duration >= tEnOel))) or tEnOel == 0
    IOelBiasPu = 0
elseif (IOelRefPu == IInstPu and (IOelRefPu > IOelActPu + IThOffPu for a duration > tOff)) or VtFiltPu < VtResetPu
    IOelBiasPu = IResetPu
else
    IOelBiasPu = 0

The SCL UEL activation logic has three inputs (from top to bottom, IUelActPu, tErr, IUelRefPu) and one output (IUelBiasPu) calculated as follows :

if tErr <= 0 or (IUelActPu > IUelRefPu for a duration >= tEnUel) or tEnUel == 0
    IUelBiasPu = 0
elseif IRefPu == IInstUelPu and (IUelRefPu > IUelActPu + IThOffPu for a duration > tOff)
    IUelBiasPu = IResetPu
else
    IUelBiasPu = 0

The SCL reference logic has two inputs (from top to bottom, IPRefPu, I’RefPu) and one output (IRefPu) calculated as follows :

if KPRef > 0 and abs(I'RefPu) > abs(IPRefPu)
    IRefPu = sqrt(I'RefPu ^ 2 - IPRefPu ^ 2)
else
    IRefPu = I'RefPu

Open source implementations

This model has been successfully implemented in :

Software URL Language Open-Source License Last consulted date Comments
Dynawo Link Modelica MPL v2.0 09/10/2024  

References

  1. of Electrical, T. I., & Engineers, E. (2016). IEEE recommended practice for excitation system models for power system stability studies . IEEE Std 421.5-2016. https://home.engineering.iastate.edu/ jdm/ee554/IEEEstd421.5-2016RecPracExSysModsPwrSysStabStudies.pdf
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